enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
vcpu 0 0 0 1000000000 0 0 50000 Y
wifi32k 1 1 0 32768 0 0 50000 Y
xtal 8 8 0 24000000 0 0 50000 Y
c11086c0.pwm#mux1 0 0 0 24000000 0 0 50000 Y
ao_cts_oscin 1 1 0 24000000 0 0 50000 N
ao_32k_pre 1 1 0 24000000 0 0 50000 Y
ao_32k_div 1 1 0 32768 0 0 50000 Y
ao_32k_sel 1 1 0 32768 0 0 50000 Y
ao_32k 1 1 0 32768 0 0 50000 Y
ao_cts_rtc_oscin 1 1 0 32768 0 0 50000 Y
ao_cts_cec 1 1 0 32768 0 0 50000 Y
hdmi_sel 0 0 0 24000000 0 0 50000 Y
hdmi_div 0 0 0 24000000 0 0 50000 Y
hdmi 0 0 0 24000000 0 0 50000 Y
gp0_pll_dco 0 0 0 1488000000 0 0 50000 N
gp0_pll 0 0 0 744000000 0 0 50000 Y
sys_pll_dco 0 0 0 1536000000 0 0 50000 N
sys_pll 0 0 0 1536000000 0 0 50000 Y
fixed_pll_dco 1 1 0 2000000000 0 0 50000 Y
fixed_pll 4 4 0 2000000000 0 0 50000 Y
fclk_div7_div 0 0 0 285714285 0 0 50000 Y
fclk_div7 0 0 0 285714285 0 0 50000 N
fclk_div5_div 0 0 0 400000000 0 0 50000 Y
fclk_div5 0 0 0 400000000 0 0 50000 N
fclk_div4_div 1 1 0 500000000 0 0 50000 Y
fclk_div4 3 3 0 500000000 0 0 50000 Y
mali_0_sel 0 0 0 500000000 0 0 50000 Y
mali_0_div 0 0 0 125000000 0 0 50000 Y
mali_0 0 0 0 125000000 0 0 50000 N
mali 0 0 0 125000000 0 0 50000 Y
mali_1_sel 0 0 0 500000000 0 0 50000 Y
mali_1_div 0 0 0 500000000 0 0 50000 Y
mali_1 0 0 0 500000000 0 0 50000 N
c11086c0.pwm#mux0 1 1 0 500000000 0 0 50000 Y
vdec_hevc_sel 0 0 0 500000000 0 0 50000 Y
vdec_hevc_div 0 0 0 500000000 0 0 50000 Y
vdec_hevc 0 0 0 500000000 0 0 50000 N
vapb_1_sel 0 0 0 500000000 0 0 50000 Y
vapb_1_div 0 0 0 500000000 0 0 50000 Y
vapb_1 0 0 0 500000000 0 0 50000 N
vapb_0_sel 1 1 0 500000000 0 0 50000 Y
vapb_0_div 1 1 0 250000000 0 0 50000 Y
vapb_0 1 1 0 250000000 0 0 50000 Y
vapb_sel 1 1 0 250000000 0 0 50000 Y
vapb 1 1 0 250000000 0 0 50000 Y
vpu_1_sel 0 0 0 500000000 0 0 50000 Y
vpu_1_div 0 0 0 500000000 0 0 50000 Y
vpu_1 0 0 0 500000000 0 0 50000 N
mpeg_clk_sel 1 1 0 500000000 0 0 50000 Y
mpeg_clk_div 1 1 0 166666667 0 0 50000 Y
clk81 24 24 0 166666667 0 0 50000 Y
ao_clk81 0 0 0 166666667 0 0 50000 Y
ir_blaster_ao 0 0 0 166666667 0 0 50000 Y
uart2_ao 0 0 0 166666667 0 0 50000 Y
uart1_ao 1 1 0 166666667 0 0 50000 Y
i2c_slave_ao 0 0 0 166666667 0 0 50000 Y
i2c_master_ao 0 0 0 166666667 0 0 50000 Y
remote_ao 0 0 0 166666667 0 0 50000 Y
gxbb_emmc_c 1 1 0 166666667 0 0 50000 Y
gxbb_emmc_b 1 1 0 166666667 0 0 50000 Y
gxbb_emmc_a 1 1 0 166666667 0 0 50000 Y
gxbb_ao_i2c 0 0 0 166666667 0 0 50000 Y
gxbb_ao_iface 0 0 0 166666667 0 0 50000 Y
gxbb_ao_ahb_bus 0 0 0 166666667 0 0 50000 Y
gxbb_ao_ahb_sram 0 0 0 166666667 0 0 50000 Y
gxbb_ao_media_cpu 0 0 0 166666667 0 0 50000 Y
gxbb_edp 0 0 0 166666667 0 0 50000 Y
gxbb_vclk_other 0 0 0 166666667 0 0 50000 N
gxbb_vclk2_vencl 0 0 0 166666667 0 0 50000 N
gxbb_vclk2_venclmcc 0 0 0 166666667 0 0 50000 Y
gxbb_gclk_venci_int1 0 0 0 166666667 0 0 50000 N
gxbb_rng1 0 0 0 166666667 0 0 50000 N
gxbb_enc480p 0 0 0 166666667 0 0 50000 N
gxbb_iec958_gate 0 0 0 166666667 0 0 50000 N
gxbb_aoclk_gate 1 1 0 166666667 0 0 50000 Y
gxbb_dac_clk 0 0 0 166666667 0 0 50000 N
gxbb_gclk_vencp_int 0 0 0 166666667 0 0 50000 Y
gxbb_gclk_venci_int0 1 1 0 166666667 0 0 50000 Y
gxbb_vclk2_vencp1 0 0 0 166666667 0 0 50000 Y
gxbb_vclk2_vencp0 0 0 0 166666667 0 0 50000 N
gxbb_vclk2_venci1 0 0 0 166666667 0 0 50000 N
gxbb_vclk2_venci0 0 0 0 166666667 0 0 50000 N
gxbb_clk81_a53 0 0 0 166666667 0 0 50000 Y
gxbb_sec_ahb_ahb3_bridge 0 0 0 166666667 0 0 50000 Y
gxbb_vpu_intr 0 0 0 166666667 0 0 50000 Y
gxbb_sana 0 0 0 166666667 0 0 50000 Y
gxbb_uart2 0 0 0 166666667 0 0 50000 N
gxbb_dvin 0 0 0 166666667 0 0 50000 N
gxbb_mmc_pclk 0 0 0 166666667 0 0 50000 Y
gxbb_usb0_ddr_bridge 1 1 0 166666667 0 0 50000 Y
gxbb_usb1_ddr_bridge 1 1 0 166666667 0 0 50000 Y
gxbb_hdmi_pclk 2 2 0 166666667 0 0 50000 Y
gxbb_hdmi_intr_sync 0 0 0 166666667 0 0 50000 Y
gxbb_ahb_ctrl_bus 0 0 0 166666667 0 0 50000 Y
gxbb_ahb_data_bus 0 0 0 166666667 0 0 50000 Y
gxbb_boot_rom 0 0 0 166666667 0 0 50000 Y
gxbb_efuse 1 1 0 166666667 0 0 50000 Y
gxbb_ahb_arb0 0 0 0 166666667 0 0 50000 N
gxbb_vdin1 0 0 0 166666667 0 0 50000 Y
gxbb_usb 2 2 0 166666667 0 0 50000 Y
gxbb_dos_parser 1 1 0 166666667 0 0 50000 Y
gxbb_nand 0 0 0 166666667 0 0 50000 Y
gxbb_reset 0 0 0 166666667 0 0 50000 Y
gxbb_usb1 1 1 0 166666667 0 0 50000 Y
gxbb_usb0 1 1 0 166666667 0 0 50000 Y
gxbb_g2d 0 0 0 166666667 0 0 50000 N
gxbb_uart1 0 0 0 166666667 0 0 50000 N
gxbb_aiu 1 1 0 166666667 0 0 50000 Y
gxbb_aiu_glue 3 3 0 166666667 0 0 50000 Y
gxbb_adc 0 0 0 166666667 0 0 50000 N
gxbb_mixer_iface 1 1 0 166666667 0 0 50000 Y
gxbb_mixer 0 0 0 166666667 0 0 50000 N
gxbb_aififo2 0 0 0 166666667 0 0 50000 N
gxbb_amclk 0 0 0 166666667 0 0 50000 N
gxbb_i2s_out 3 3 0 166666667 0 0 50000 Y
gxbb_iec958 0 0 0 166666667 0 0 50000 N
gxbb_blkmv 0 0 0 166666667 0 0 50000 Y
gxbb_demux 0 0 0 166666667 0 0 50000 N
gxbb_eth 1 1 0 166666667 0 0 50000 Y
gxbb_i2s_spdif 0 0 0 166666667 0 0 50000 N
gxbb_spi 0 0 0 166666667 0 0 50000 N
gxbb_assist_misc 0 0 0 166666667 0 0 50000 Y
gxbb_hiu_iface 0 0 0 166666667 0 0 50000 Y
gxbb_abuf 0 0 0 166666667 0 0 50000 Y
gxbb_sdio 0 0 0 166666667 0 0 50000 Y
gxbb_async_fifo 0 0 0 166666667 0 0 50000 N
gxbb_stream 0 0 0 166666667 0 0 50000 N
gxbb_sdhc 0 0 0 166666667 0 0 50000 Y
gxbb_uart0 1 1 0 166666667 0 0 50000 Y
gxbb_rng0 1 1 0 166666667 0 0 50000 Y
gxbb_smart_card 0 0 0 166666667 0 0 50000 N
gxbb_sar_adc 1 1 0 166666667 0 0 50000 Y
gxbb_i2c 1 1 0 166666667 0 0 50000 Y
gxbb_spicc 0 0 0 166666667 0 0 50000 N
gxbb_periphs 0 0 0 166666667 0 0 50000 Y
gxbb_pl301 0 0 0 166666667 0 0 50000 Y
gxbb_isa 0 0 0 166666667 0 0 50000 Y
gxbb_dos 1 1 0 166666667 0 0 50000 Y
gxbb_ddr 0 0 0 166666667 0 0 50000 Y
fclk_div3_div 1 1 0 666666666 0 0 50000 Y
fclk_div3 3 3 0 666666666 0 0 50000 Y
vdec_1_sel 1 1 0 666666666 0 0 50000 Y
vdec_1_div 1 1 0 666666666 0 0 50000 Y
vdec_1 1 1 0 666666666 0 0 50000 Y
vpu_0_sel 1 1 0 666666666 0 0 50000 Y
vpu_0_div 1 1 0 666666666 0 0 50000 Y
vpu_0 1 1 0 666666666 0 0 50000 Y
vpu 1 1 0 666666666 0 0 50000 Y
fclk_div2_div 1 1 0 1000000000 0 0 50000 Y
fclk_div2 5 5 0 1000000000 0 0 50000 Y
d0070000.mmc#mux 1 1 0 1000000000 0 0 50000 Y
d0070000.mmc#div 1 1 0 50000000 0 0 50000 Y
c9410000.ethernet#m250_sel 1 1 0 1000000000 0 0 50000 Y
c9410000.ethernet#m250_div 1 1 0 250000000 0 0 50000 Y
c9410000.ethernet#fixed_div2 1 1 0 125000000 0 0 50000 Y
c9410000.ethernet#rgmii_tx_en 1 1 0 125000000 0 0 50000 Y
d0074000.mmc#mux 1 1 0 1000000000 0 0 50000 Y
d0074000.mmc#div 1 1 0 200000000 0 0 50000 Y
d0072000.mmc#mux 1 1 0 1000000000 0 0 50000 Y
d0072000.mmc#div 1 1 0 25000000 0 0 50000 Y
mpll_prediv 1 1 0 2000000000 0 0 50000 Y
mpll0_div 1 1 0 294909641 0 0 50000 Y
mpll0 1 1 0 294909641 0 0 50000 Y
cts_amclk_sel 1 1 0 294909641 0 0 50000 Y
cts_amclk_div 1 1 0 12287902 0 0 50000 Y
cts_amclk 1 1 0 12287902 0 0 50000 Y
cts_mclk_i958_sel 0 0 0 294909641 0 0 50000 Y
cts_mclk_i958_div 0 0 0 12287902 0 0 50000 Y
cts_mclk_i958 0 0 0 12287902 0 0 50000 N
cts_i958 0 0 0 12287902 0 0 50000 Y
mpll1_div 0 0 0 270948751 0 0 50000 Y
mpll1 0 0 0 270948751 0 0 50000 N
mpll2_div 0 0 0 393212855 0 0 50000 Y
mpll2 0 0 0 393212855 0 0 50000 N
gen_clk_sel 0 0 0 24000000 0 0 50000 Y
gen_clk_div 0 0 0 24000000 0 0 50000 Y
gen_clk 0 0 0 24000000 0 0 50000 N
hdmi_pll_pre_mult 0 0 0 48000000 0 0 50000 Y
hdmi_pll_dco 0 0 0 2970000000 0 0 50000 Y
hdmi_pll_od 0 0 0 2970000000 0 0 50000 Y
hdmi_pll_od2 0 0 0 1485000000 0 0 50000 Y
hdmi_pll 0 0 0 742500000 0 0 50000 Y
vid_pll_div 0 0 0 148500000 0 0 50000 Y
vid_pll_sel 0 0 0 148500000 0 0 50000 Y
vid_pll 0 0 0 148500000 0 0 50000 Y
vclk2_sel 0 0 0 148500000 0 0 50000 Y
vclk2_input 0 0 0 148500000 0 0 50000 N
vclk2_div 0 0 0 74250000 0 0 50000 Y
vclk2 0 0 0 74250000 0 0 50000 N
vclk2_div1 0 0 0 74250000 0 0 50000 N
vclk2_div12_en 0 0 0 74250000 0 0 50000 N
vclk2_div12 0 0 0 6187500 0 0 50000 Y
vclk2_div6_en 0 0 0 74250000 0 0 50000 N
vclk2_div6 0 0 0 12375000 0 0 50000 Y
vclk2_div4_en 0 0 0 74250000 0 0 50000 N
vclk2_div4 0 0 0 18562500 0 0 50000 Y
vclk2_div2_en 0 0 0 74250000 0 0 50000 N
vclk2_div2 0 0 0 37125000 0 0 50000 Y
vclk_sel 0 0 0 148500000 0 0 50000 Y
vclk_input 0 0 0 148500000 0 0 50000 N
vclk_div 0 0 0 148500000 0 0 50000 Y
vclk 0 0 0 148500000 0 0 50000 Y
vclk_div1 0 0 0 148500000 0 0 50000 Y
hdmi_tx_sel 0 0 0 148500000 0 0 50000 Y
hdmi_tx 0 0 0 148500000 0 0 50000 Y
cts_vdac_sel 0 0 0 148500000 0 0 50000 Y
cts_vdac 0 0 0 148500000 0 0 50000 N
cts_encp_sel 0 0 0 148500000 0 0 50000 Y
cts_encp 0 0 0 148500000 0 0 50000 Y
cts_enci_sel 0 0 0 148500000 0 0 50000 Y
cts_enci 0 0 0 148500000 0 0 50000 N
vclk_div12_en 0 0 0 148500000 0 0 50000 N
vclk_div12 0 0 0 12375000 0 0 50000 Y
vclk_div6_en 0 0 0 148500000 0 0 50000 N
vclk_div6 0 0 0 24750000 0 0 50000 Y
vclk_div4_en 0 0 0 148500000 0 0 50000 Y
vclk_div4 0 0 0 37125000 0 0 50000 Y
vclk_div2_en 0 0 0 148500000 0 0 50000 Y
vclk_div2 0 0 0 74250000 0 0 50000 Y
sd_emmc_c_clk0_sel 0 0 0 24000000 0 0 50000 Y
sd_emmc_c_clk0_div 0 0 0 24000000 0 0 50000 Y
sd_emmc_c_clk0 0 0 0 24000000 0 0 50000 N
sd_emmc_b_clk0_sel 0 0 0 24000000 0 0 50000 Y
sd_emmc_b_clk0_div 0 0 0 24000000 0 0 50000 Y
sd_emmc_b_clk0 0 0 0 24000000 0 0 50000 N
sd_emmc_a_clk0_sel 0 0 0 24000000 0 0 50000 Y
sd_emmc_a_clk0_div 0 0 0 24000000 0 0 50000 Y
sd_emmc_a_clk0 0 0 0 24000000 0 0 50000 N
32k_clk_sel 0 0 0 24000000 0 0 50000 Y
32k_clk_div 0 0 0 24000000 0 0 50000 Y
32k_clk 0 0 0 24000000 0 0 50000 N
sar_adc_clk_sel 1 1 0 24000000 0 0 50000 Y
sar_adc_clk_div 1 1 0 1142858 0 0 50000 Y
sar_adc_clk 1 1 0 1142858 0 0 50000 Y